{"id":974,"date":"2020-11-13T20:59:16","date_gmt":"2020-11-13T20:59:16","guid":{"rendered":"https:\/\/pdp2011.sytse.net\/wordpress\/?page_id=974"},"modified":"2020-11-13T20:59:16","modified_gmt":"2020-11-13T20:59:16","slug":"mncad","status":"publish","type":"page","link":"https:\/\/pdp2011.sytse.net\/wordpress\/pdp-11\/minc\/mncad\/","title":{"rendered":"MNCAD"},"content":{"rendered":"\n<figure class=\"wp-block-image size-large\"><img decoding=\"async\" src=\"https:\/\/pdp2011.sytse.net\/wordpress\/wp-content\/uploads\/2020\/11\/Screenshot-2020-11-12-at-21.44.52-1024x844.png\" alt=\"\" class=\"wp-image-975\"\/><\/figure>\n\n\n\n<p>MNCAD is the A\/D converter. It has 8 single-ended A\/D channels on the module itself, and  handles up to a total of 64 A\/D single-ended and differential channels &#8211; controlling the multiplexer and pre-amplifier cards necessary. <\/p>\n\n\n\n<pre class=\"wp-block-preformatted\">MNCAD   CSR 171000   VEC 400\/404      BR 6<\/pre>\n\n\n\n<p>MNCAD has two registers; the CSR @ 171000, and BUF @ 171002. The CSR mostly follows the conventional layout &#8211; a done bit 7, an interrupt enable bit 6, a go bit 0. Unusual however is that this pattern is repeated in the high byte, and with a separate interrupt vector. The BUF register holds the result of the last conversion. There is a provision for detecting overrun; if the register is not read before a new conversion is stored, an (the?) error bit will be set.<\/p>\n\n\n\n<p><strong>MNCAD CSR<\/strong><\/p>\n\n\n\n<figure class=\"wp-block-table\"><style> table, th, td { vertical-align: top; } <\/style> <table><colgroup><col style=\"width:15%;\"><\/colgroup><tbody>\n\n<tr><td>15<\/td><td>err (R\/W) <br>The err bit is set when the go bit is set before the previous operation has finished (&#8216;if go=&#8217;1&#8242; and done=&#8217;0&#8242; then err=&#8217;1&#8217;). <br>It is also set when the BUF register has not been read and a new result is being stored into the BUF register (?). <\/td>\n\n<\/tr><tr><td>14<\/td><td>errie (R\/W)<br>The errie bit, when set, enables interrupts when the err bit is set. The interrupt vector used will be the base vector + 4.<\/td><\/tr>\n\n<tr><td>13:8<\/td><td>muxch (R\/W)<br>The channel for the next A\/D operation. <\/td><\/tr>\n\n<tr><td>7<\/td><td>done (R\/W)<br>Done is set when the last operation has completed.<\/td><\/tr>\n\n<tr><td>6<\/td><td>ie (R\/W)<br>The ie bit, when set, enable interrupts when the done bit is set. The interrupt vector is the base vector.<\/td><\/tr>\n\n<tr><td>5<\/td><td>clkovf (R\/W)<br>When set, overflow of the associated MNCKW clock module will trigger the go bit and thus start conversion.<\/td><\/tr>\n\n<tr><td>4<\/td><td>ext (R\/W)<br>When set, external trigger sources are enabled to start conversion. The external trigger sources are: the ST1 on the associated MNCKW clock module.<\/td><\/tr>\n\n<tr><td>3<\/td><td>enable_id (R\/W)<br>When set, the top 4 bits of the MNCAD BUF register will get the gain setting or type code of the A\/D channel after the next conversion.<\/td><\/tr>\n\n<tr><td>2<\/td><td>maint (R\/W)<br>When set and muxch is 0, the next conversion will be read 0 (all zeroes). When set and muxch is 1, the next conversion will be read 4095 (all ones). <\/td><\/tr>\n\n<tr><td>1<\/td><td>nxc (R\/O)<br>The nxc bit is 1 when the muxch field refers to a channel that is not available. Otherwise, it is 0.<\/td><\/tr><tr><td>0<\/td><td>go (R\/W)<br>When written &#8216;1&#8217;, MNCAD will start a new conversion. When read &#8216;1&#8217;, MNCAD is busy. When &#8216;0&#8217;, MNCAD is idle.<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<p><strong>MNCAD BUF<\/strong><\/p>\n\n\n\n<figure class=\"wp-block-table\"><style> table, th, td { vertical-align: top; } <\/style> <table><colgroup><col style=\"width:15%;\"><\/colgroup><tbody>\n<tr><td>15:12<\/td><td>code (R\/O)<br>Zero (when ADCSR enable_id is &#8216;0&#8217;) or channel code for the last conversion result (when ADCSR enable_id is &#8216;1&#8217;)<\/td><\/tr>\n<tr><td>11:0<\/td><td>buf (R\/O)<br>The results of the last conversion.<br>\nReading the buffer resets the ADCSR done bit.<\/td><\/tr>\n<\/tbody><\/table><\/figure>\n\n\n\n<p><strong>Information sources<\/strong><br>The information in this page is mainly based on the VMNA listing.<\/p>\n\n\n\n<p><strong>Side channel<\/strong><br>The MNCAD communicates to MNCAM (multiplexer), MNCAG (preamplifier) and MNCTP (thermocouple preamplifier) modules via a side channel. It is used to determine the configuration and the setting of front panel switches (in case of MNCAG); and also to write the programmable gain registers in MNCAG and MNCTP.<\/p>\n\n\n\n<p>To use the side channel, software writes a value of o&#8217;77&#8217; into the muxch register in the MNCAD CRS; followed by the desired code, and then the number of the target channel. To scan the configuration, software should program a code of o&#8217;01&#8217; into all channels and start a conversion with the ADCSR enable_id bit set; the conversion result in ADBUF will then show the type of the channel in the bits 15:12 according to the following table:<\/p>\n\n\n\n<figure class=\"wp-block-table\"><table><tbody><tr><td>code<\/td><td>type<\/td><\/tr><tr><td>0000<\/td><td>Single ended channel (MNCAD or MNCAM)<\/td><\/tr><tr><td>0001<\/td><td>MNCTP channel<\/td><\/tr><tr><td>0010<\/td><td>Differential channel (MNCAD or MNCAM)<\/td><\/tr><tr><td>0011<\/td><td>unused<\/td><\/tr><tr><td>0100-0111<\/td><td>MNCAG, channel dial set to A<\/td><\/tr><tr><td>1000-1011<\/td><td>MNCAG, channel dial set to R<\/td><\/tr><tr><td>1100-1111<\/td><td>MNCAG, channel dial set to V<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<p><strong>Unknown\/Missing information<\/strong><br>From the VMNA listing, it appears to be possible to run more than one MNCAD module in a system, but it is not clear if the software would support this. Probably the only reason to have more than one module would be to speed up A\/D conversions.<\/p>\n\n\n\n<p>There is no information about the MNCTP modules; these appear to implement a gain setting register of 4 bits wide, but it is not clear what the meaning of the bits is. MNCTP seems to be of a later date than the available manuals, no description, schematics or manuals have so far been found.<\/p>\n\n\n\n<p>Also, MNCAG is missing from the currently available schematics.<\/p>\n\n\n\n<p><strong>Implementation status<\/strong><br>The current implementation is complete for the maximum of 64 single-ended channels. Software will apply a bias based on a -5.12V to +5.12V range; however, the current FPGA board A\/D frontends are set up for 0V to +3.3V (DE10-Lite and DE0-Nano). The A\/D frontends will implement the &#8216;real&#8217; channels on the board in the lower numbered channels, and set up a multiplexer to allow the top.vhd module to insert other values into the A\/D.<\/p>\n\n\n\n<p>Other channel types besides single-ended are possible as well, but configuration for now can only be done by directly editing the sources. The interface between the MNCAD component and the A\/D frontends will likely change to improve this.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>MNCAD is the A\/D converter. It has 8 single-ended A\/D channels on the module itself, and handles up to a total of 64 A\/D single-ended and differential channels &#8211; controlling the multiplexer and pre-amplifier cards necessary. MNCAD CSR 171000 VEC 400\/404 BR 6 MNCAD has two registers; the CSR @ 171000, and BUF @ 171002. [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":988,"menu_order":110,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-974","page","type-page","status-publish","hentry","missing-thumbnail"],"_links":{"self":[{"href":"https:\/\/pdp2011.sytse.net\/wordpress\/wp-json\/wp\/v2\/pages\/974","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pdp2011.sytse.net\/wordpress\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/pdp2011.sytse.net\/wordpress\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/pdp2011.sytse.net\/wordpress\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/pdp2011.sytse.net\/wordpress\/wp-json\/wp\/v2\/comments?post=974"}],"version-history":[{"count":0,"href":"https:\/\/pdp2011.sytse.net\/wordpress\/wp-json\/wp\/v2\/pages\/974\/revisions"}],"up":[{"embeddable":true,"href":"https:\/\/pdp2011.sytse.net\/wordpress\/wp-json\/wp\/v2\/pages\/988"}],"wp:attachment":[{"href":"https:\/\/pdp2011.sytse.net\/wordpress\/wp-json\/wp\/v2\/media?parent=974"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}