MNCAD is the A/D converter. It has 8 single-ended A/D channels on the module itself, and handles up to a total of 64 A/D single-ended and differential channels – controlling the multiplexer and pre-amplifier cards necessary.
MNCAD CSR 171000 VEC 400/404 BR 6
MNCAD has two registers; the CSR @ 171000, and BUF @ 171002. The CSR mostly follows the conventional layout – a done bit 7, an interrupt enable bit 6, a go bit 0. Unusual however is that this pattern is repeated in the high byte, and with a separate interrupt vector. The BUF register holds the result of the last conversion. There is a provision for detecting overrun; if the register is not read before a new conversion is stored, an (the?) error bit will be set.
From the VMNA listing, it appears to be possible to have more than one MNCAD in one system. It is however not clear in what use cases you would use a second module, and if the software would support that.
The err bit is set when the go bit is set before the previous operation has finished (‘if go=’1′ and done=’0′ then err=’1’).
It is also set when the BUF register has not been read and a new result is being stored into the BUF register (?).
The errie bit, when set, enables interrupts when the err bit is set. The interrupt vector used will be the base vector + 4.
The channel for the next A/D operation.
Done is set when the last operation has completed.
The ie bit, when set, enable interrupts when the done bit is set. The interrupt vector is the base vector.
When set, overflow of the associated MNCKW clock module will trigger the go bit and thus start conversion.
When set, external trigger sources are enabled to start conversion. The external trigger sources are: the ST1 on the associated MNCKW clock module.
Not clear what this does.
When set and muxch is 0, the next conversion will be read 0 (all zeroes). When set and muxch is 1, the next conversion will be read 4095 (all ones).
The nxc bit is 1 when the muxch field refers to a channel that is not available. Otherwise, it is 0.
When written ‘1’, MNCAD will start a new conversion. When read ‘1’, MNCAD is busy. When ‘0’, MNCAD is idle.
|15:12||unused (R/O) Zero|
The results of the last conversion.
Reading the buffer resets the ADCSR done bit.
The information in this page is mainly based on the VMNA listing.
There is a side channel by which the multiplexer and pre-amplifier modules are programmed. There is currently no information on how this works. Presumably, this might be used to inform the A/D module and software of different voltage ranges than the default.
Also, it is not clear what the enable_id bit in the CSR is for.
The current implementation works for channels 0-7; the software assumes these to be the built-in single ended channels on the MNCAD module. It appears that higher numbered channels work as well and will also be assumed to be single ended. Software will apply a bias based on a -5.12V to +5.12V range; however, the current FPGA board A/D frontends are set up for 0V to +3.3V (DE10-Lite and DE0-Nano).