The MNCDO is a digital output for up to 16 lines. The lines can be used individually, or in two groups of 8, or in one group of 16. For the last two variants, there are two strobe signals to signal update events.

MNCDO   CSR 171260     VEC 340      BR 4

MNCDO has two registers: a CSR @ 171260, and the DOR Data Output Register @ 171262. The CSR is relatively simple, compared to most MINC modules – the MNCDO only uses one interrupt vector.

More than one MNCDO can be present in a system; their addressing should directly follow the first module. There is no clear limit to the number of modules that can be added.


8maint (w/o)
reads as 0
when written ‘1’, simulates a pulse on the reply input. Possibly this should only work when a byte access is done.
7done (r/w)
the done bit will be set when the external reply signal is pulsed. It is cleared by writing to the DOR register, or by direct writing to the CSR.
When set, if the ie bit is set, an interrupt will be triggered.
6ie (r/w)
interrupt enable; when set, an interrupt will be triggered when the done bit is set.
4defeat panel sw (r/w)
presumably, this bit disables the front panel signal invert switch.
3pos edge reply (r/w)
presumably, this bit reverses the polarity of the reply input.

Information sources
The information in this page is mainly based on the VMNE test output and the schematic.

Unknown/Missing information
There might be more CSR bits than I’ve found so far; and the bits 4 and 3 are just based on the schematic – ie, not verified by test software etc.

Implementation status
The current implementation passes the VMNE test without error, and can be used with MINC BASIC. The CSR bits 4 and 3 are not currently implemented