As a byproduct of the PiDP-11 console support, I’ve defined a more or less ‘standard’ pin layout for the 40-pin connector on most of the Intel/Altera/Terasic FPGA boards – obviously carrying all the signals for the console itself, but also for the most basic peripherals that all PDP2011 systems need: a serial port for the […]

RSTS and J-11

Some time ago, Paul Koning contacted me about the issue that RSTS did not correctly detect the CPU type when the cpu was configured as a J-11 type – 11/84 or 11/94. He had already identified a problem in the cpu sources: the MFPT instruction would set the CPU code in the primary register set, […]

FPU and DEUNA fixes

Since I found the problem with the BAE register in the RH70 that prevented RSX-11MP from running, I’ve been working on straightening out the timing between the CPU and the main memory. It’s nowhere near finished, but the first tests show that when it is, the CPU will be capable of much higher speed – […]